1. Field of the Invention
The present invention relates generally to the field of integrated circuit testing and design, more particularly, to a method and system for creation of memory array bitmaps for an integrated circuit chip design.
2. Description of the Related Art
Present electronic design systems consist of software tools running on a digital computer that assist a designer in the creation and verification of complex integrated circuit (IC) chip designs. Electronic computer-aided design (ECAD) systems are widely used in designing these IC chips. In particular, ECAD systems are used to generate data descriptive of the entire circuit layout as well as the layout of individual circuit cells. Since each cell often contains a large number of circuit elements and interconnections among the elements, ECAD systems have become an indispensable tool in the design of integrated circuits. In addition to generating layout design, some types of ECAD systems generate mask pattern data using circuit layout data. The mask pattern data is used to control various exposure processes necessary for the IC chip""s manufacture.
Layout tools forming part of the ECAD systems are used to lay out a chip design onto silicon. The resulting chip layout may be represented in the form of a netlist, i.e., a list of low-level design cells and the interconnections between them. The chip layout may also be represented in the form of a physical design file representing multiple layers of polygons. Once the design is completed, the part is xe2x80x9ctaped outxe2x80x9d (i.e., files representing the chip are written to tape or disk). One format used for such files is the GDSII format. A mask house then makes photomasks to manufacture the chip.
Both memory chips and logic chips require production monitoring and testing. Production monitoring is performed using xe2x80x9cin-linexe2x80x9d inspection equipment, and production testing is performed using xe2x80x9cend-of-linexe2x80x9d test equipment. In-line inspection equipment inspects entire semiconductor wafers, each of which may have formed thereon hundreds of chips. End-of-line test equipment performs xe2x80x9cbinsort functional testxe2x80x9d on semiconductor wafers in which the pads of chips are contacted and the chips xe2x80x9cexercised.xe2x80x9d At the conclusion of functional test, parts are xe2x80x9cbinnedxe2x80x9d (typically, placed in different categories within an electronic record) according to the test results.
Apart from production testing is failure analysis. Failure analysis attempts to identify the cause of failures of chips of a particular chip design after those failures have been detected during production (or prototype) testing. Failure analysis may typically require more detailed failure information than just a bin code. Detailed failure information is typically obtained by retesting a limited number of packaged parts. These various forms of testing represent tester data.
FIG. 1 represents a current method of logical to physical array bitmap translations 10 for an IC chip that gathers the tester data 14 and detailed design profile data and design algorithms 11 to reproduce the cells and to show their placement relative to each other. This logical to physical conversion has no actual chip physical X,Y coordinates, cell size, spacings or other reference to chip and array origins. After the array bitmap is created for the IC chip, a verification process begins which usually is an iterative process of several changes to the translation code as it relates to the design profiles and algorithms 11 to produce an accurate bitmap, wherein these bitmaps are then compressed and converted to binary formats for storage 13. This data compression process is necessary because of the huge maps of passing and failing cells. After the maps are compressed, a pattern recognition process 15 uses a pattern recognition profile 16 to identify memory fail pattens like Wordline, Bitline, Single Cell Fails, Vertical and Horizontal Pairs, and clusters and partials of these patterns. The automatic pattern recognition section 15 then processes the data to an APRC (automated pattern recognition code) database 19. Still a logical to physical transistor 21 converts the physical map to the actual design coordinates and physical data location. This requires more design data and the creation of another design profile and related algorithms 20 to match shapes to defect overlays 18. In summary, prior processing of array bitmaps requires substantial engineering overhead expense and data storage capacity 13 and 19, has long turn around times, and is prone to human error. Additionally, these maps are typically not directly usable in display tools or for driver tool navigation as used in failure analysis laboratories.
Prior teachings that have attempted to automate this process include U.S. Pat. No. 6,185,707, entitled xe2x80x98IC test software system for mapping logical functional test data of logic integrated circuits to physical representation.xe2x80x99 This disclosure describes how xe2x80x98logicxe2x80x99 net-names are converted to physical shapes for defect overlays but does not describe or provide any way for arrays to be translated and overlayed. Typically logic has test models that create the net names and devices for logic testing which enables an easy logical to physical conversion. Embedded arrays are not supported in the same way. The present U.S. Pat. No. 6,185,707 teaches of ways of determining and displaying X, Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X, Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. However, this method is limited to only the logic portions of the chip and provides no way of doing a comparable logical to physical conversion of failing embedded memory cells. Thus, there is need in the IC chip design arts for a method and system that converts failing memory cells to created logic nets and uses multiple nets to create an intersection of the metal shapes to locate a memory cell.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional methods of integrated circuit testing and creation of array bitmaps, the present invention has been devised, and it is an object of the present invention to provide a method and system for automatically creating these bitmaps using a logical to physical server.
To attain the object suggested above, there is provided, according to one aspect of the invention, a method that generates array bitmaps using the binary address and failing data bits collected during test as input and translates this directly to physical location in either GDSII or GL1 physical design formats using the logical to physical server forming part of an ECAD system.
The system of the invention uses the logical to physical data generated during layout versus schematic (LVS) checking of a design. In such a design, every device in the IC chip has a full pin path name to each port on that device. Most, if not all arrays cells today are of standard cell design and their physical layout is very systematic and symmetrical. The wordline and bitline selects physical orientation and direction are also placed to optimize minimal space and maximize performance. The result is that these select lines pass directly over the cell to be selected. This form of layout provides and enables efficient processes to be used during the logical to physical bitmap creation.
The invention maps defects to physical locations of a memory array and logically tests the memory array to produce a binary memory defect address. The invention then converts the binary memory defect address into a logical bitline net name and a logical wordline net name. The invention performs a logical to physical translation on the logical bitline net name to produce a physical bitline net name and performs a logical to physical translation on the logical wordline net name to produce a physical wordline net name. Next the invention merges the physical bitline net name and the physical wordline net name into a single physical location within the memory array.
The binary memory defect address is determined during logical testing of signals output from the memory array. The converting process uses test data and profiles that relate the binary addresses to the logical bitline net name and the logical wordline net name. The merging obtains an X coordinate from the physical bitline net name and a Y coordinate from the physical wordline net name and combines the X coordinate and the Y coordinate to produce the single physical location. The invention stores a series of physical locations relating to a plurality of defects in a database which includes only physical locations of defects in the memory array. The invention also locates a metal shape that is closest to the physical location.
The invention can be applied to many logic and memory circuits, which have many embedded arrays which necessitates volume array fail data collection, efficient and fast bitmap processing, and translation to formats usable by diagnostic and failure analysis tool sets for identification of root cause fail mechanisms. The method of the invention does not require design information gathering and creation of profiles and algorithms for each design. This eliminates the huge engineering overhead, is a standard process for each design, has faster turn around time, is not prone to human error, and generates efficient physical array bitmaps that are usable by downstream overlay, net highlight, and navigation tools. This yields cost competitive designs, as well as enhanced performance and reliability of these designs in the next generation of logic and memory circuits.